284 articles – 2152 references  [version française]
Detailed view Conference proceedings
Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043, Princeton, NJ : États-Unis (1996)
Standard and ROM-based synthesis of FSMs with control flow checking capabilities
X. Wending1, R. Rochet1, R. Leveugle1, 2

This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow.
1:  CSI - CSI, INPG, Grenoble
2:  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
FSM- – control-flow-checking – sequencing-error-detection – finite-state-machine – automatic-synthesis – ROM-architecture