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Conference proceedings

Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002, Vancouver, BC : Canada (2002)

New methods for evaluating the impact of single event transients in VDSM ICs

D. Alexandrescu1, L. Anghel1, M. Nicolaidis1, 2

This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.

1:	TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
2:	IROC TECHNOLOGIES - iROc Technologies

Keyword(s) : single-event-transient – VDSM-ICs – very-deep-submicron-ICs – SET-fault-simulation-technique – probability- – combinational-logic – storage-cell

hal-00013736, version 1

http://hal.archives-ouvertes.fr/hal-00013736

oai:hal.archives-ouvertes.fr:hal-00013736

From: Lucie Torella <>

Submitted on: Thursday, 10 November 2005 13:26:34

Updated on: Friday, 24 February 2006 11:04:42