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19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Hong Kong : China (2011)

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Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)

Sébastien Le Beux1, Jelena Trajkovic2, Ian O'Connor1, Gabriela Nicolescu3

Trends in design of the next generation of Multi-Processors System on Chip (MPSoC) point to 3D integration of thousand of processing elements, requiring high performance interconnect for high throughput and low latency communications. Optical on-chip interconnects enable significantly increased bandwidth and decreased latency. They are thus considered as one of the most promising paradigms for the design of such system. However, existence of interfaces between electronic and photonic signals implies strong constraints on the layout of the 3D architecture and may impact the architecture scalability. In this paper, we propose and evaluate a possible layout for an optical Network-on-Chip used to interconnect processing elements located on different electrical layers.

1 :	INL - Institut des nanotechnologies de Lyon - Site d'Ecully
2 :	GR2M - Groupe de recherche en microélectronique et microsystèmes
3 :	EPM - Ecole Polytechnique de Montreal

inria-00618605, version 1

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Contributeur : Sébastien Le Beux <>

Soumis le : Vendredi 2 Septembre 2011, 11:50:34

Dernière modification le : Vendredi 2 Septembre 2011, 14:03:31