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10th China Semiconductor Technology International Conference 2011, CSTIC 2011, France (2011)

FPGA design with double-gate carbon nanotube transistors

Haykel Ben Jamma1, Pierre-Emmanuel Gaillardon2, Sebastien Fregonese3, Michele De Marchi2, Giovanni De Micheli4, Thomas Zimmer3, Fabien Clermidy1, Ian O'Connor2

Double-gate carbon nanotube field effect transistors (DG-CNTFETs) are novel devices showing an interesting property allowing to control the p- or n-type behavior during the device operation. This opens up the opportunity for novel design paradigms. Based on a compact physical model of these devices, we demonstrate the benefit of designing field-programmable gate arrays (FPGAs) using fine-grain DG-CNTFET logic blocs rather than traditional look-up tables and coarse-grain DG-CNTFET logic blocs. In particular, we show a reduction by 13% to 48% on average in terms of delay of FPGA benchmarks. ©The Electrochemical Society.

1:	LETI - Laboratoire d'Electronique et des Technologies de l'Information
2:	INL - Institut des nanotechnologies de Lyon - Site d'Ecully
3:	IMS - Laboratoire de l'intégration, du matériau au système
4:	EPFL - Ecole Polytechnique Fédérale de Lausanne

hal-00669403, version 1

http://hal.archives-ouvertes.fr/hal-00669403

oai:hal.archives-ouvertes.fr:hal-00669403

From: Sebastien Fregonese <>

Submitted on: Monday, 13 February 2012 11:16:55

Updated on: Monday, 13 February 2012 11:20:51