Universal Digital Radio Transmitter for Multistandard Applications
Résumé
A new low power, wideband wireless transmitter able to convert any RF signal into a constant envelope signal enabling the use of a nonlinear and efficient power amplifier is presented. In the transmitter architecture, two normalized phase signals and the envelope are separated and processed separately. A 1-bit 2nd order SD modulator codes the envelope. Quantization noise is attenuated by a S&H interpolator introducing notches at multiples of the sampling frequency. Phase and Envelope signals are recombined and upconverted directly to radio frequencies using a novel full-digital, wideband quadrature modulator. This mixer takes advantage of the 1-bit SD output. As both LOs and envelope signals are represented by two-level signals, the product of these signals (XOR function) leads to a two-level signal, which can be used as command signal in the multiplexors. Phase signals or theirs complements that are generated by a simple Inversion Block are passed through this multiplexor at the rate of driving signals. This enables to implement a high frequency, wideband mixer instead of a more complex three-input modulator. This IQ mixer is very simple to implementate as it uses only CMOS logic gates. The generation of the quadrature clock signals in the mixer is obtained by carefully design of two paths to avoid mismatch to assure an error less than 1º (only demonstrated in simulation) and the use of SR flipflops to generate correctly the complementary signal prior to the divide-by-two circuit. Two asynchronous 9-bit DACs eliminate the 10-bit high-speed digital adder at the output of the IQ modulator and the 10-bit DAC before the PA, saving power and relaxing adder design constraints. Each DAC is divided into two full binary-weighted DACs of 4 and 5 bits. This topology enables to reduce the size ratios between the most and least significant bits related to a classic 9-bit binary-weighted structure (16 instead of 256). To test the speed and the gain control of the standalone DAC over 45 dB, a prototype DAC is designed in 0.13 ;m BiCMOS technology from STMicroelectronics together with a 1.4 GHz 9-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Over the output power range, measurements show a SFDR>25 dB with a power dissipation of 25 mW at the maximum differential output power of -3 dBm (RL=50 @). The whole transmitter is designed and implemented and a prototype transmitter is built in 0.13 μm BiCMOS STMicroelectronics process. This low cost single chip digital radio transmitter demonstrates a data rate of 1.8 GHz. The image level is measured to be -12 dBc at this sampling frequency. Dynamic range in the transmitter is 35 dB for sampling frequencies lower than 800 MHz and 25 dB for higher sampling frequencies up to 1.8 GHz. For a two-tone signal, the maximum single-ended output power is -31dBm for each tone and the power dissipation is about 35 mW. This architecture enables flexible and software-defined transmitter. Sampling frequency in the SD coder can be varied to adapt to different communications standards in terms of in-band and outof-band noise requirements and variable LO frequencies can be used. Moreover, the transmitter can adapt dynamically the output power to the power amplifier depending of the required transmitted power at the output of the PA. The transmitter has demonstrated its potential for use as a universal transmitter for applications targeting any frequency band and modulation schema up to 900 MHz (carrier frequency) and occupies a die area of 300x320 ;m2. The generated differential signal can be easily amplified by a switched-mode Power Amplifier (PA) in an efficient way because it presents constant-envelope and the PA can work in the saturation zone, which represents its optimal operation point.