Design for Reliability Techniques in Embedded Flash Memories
Techniques de Conception en Vue d'Améliorer la fiabilité des Mémoires Flash Embarquées
Résumé
Flash memories are non-volatile memories present in a growing number of integrated circuits used in portable electronic devices. The non-volatility, low power consumption and flexibility make them extremely popular. Nevertheless, the reliability is a characteristic to improve as far as area needs increase and critical applications are targeted. Effectives fault tolerance solutions that are low cost and that can be easily integrated must be found. In a first time, the work of this thesis was focused on the analysis and the study of Flash reliability. It was the occasion to establish a reliability model for a floating gate cell depending on various parameters. This model was adjusted depending
on parameters coming from a 180 nm technology. In a second time, the work was dedicated on the development of two fault tolerance techniques merging error correcting codes and redundancy. The first technique, called error correction by VT analysis, provides an extended correction capacity by analyzing the charge level of cells. A mathematical study and next, a reliability architecture have been proposed. In this study, it is supposed that a given number of redundancy resources are available to repair the memory as soon as an error is detected. The second developed technique, called hierarchical error correction, uses the fact that correction capacities can be distributed in an original
way into the memory to significantly reduce the cost usually associated with advanced error correction techniques. This code has also been integrated in a reliability architecture having some redundancy resources. A mathematical study based on Continuous Time Markov Chain has allowed to demonstrate the effectiveness of this structure. Developed techniques are alternatives solutions to standard scheme used in the industry. They allows to improve significantly the mean time to failure of a system by many times at a reasonable area cost.
on parameters coming from a 180 nm technology. In a second time, the work was dedicated on the development of two fault tolerance techniques merging error correcting codes and redundancy. The first technique, called error correction by VT analysis, provides an extended correction capacity by analyzing the charge level of cells. A mathematical study and next, a reliability architecture have been proposed. In this study, it is supposed that a given number of redundancy resources are available to repair the memory as soon as an error is detected. The second developed technique, called hierarchical error correction, uses the fact that correction capacities can be distributed in an original
way into the memory to significantly reduce the cost usually associated with advanced error correction techniques. This code has also been integrated in a reliability architecture having some redundancy resources. A mathematical study based on Continuous Time Markov Chain has allowed to demonstrate the effectiveness of this structure. Developed techniques are alternatives solutions to standard scheme used in the industry. They allows to improve significantly the mean time to failure of a system by many times at a reasonable area cost.
Les mémoires non-volatiles de type Flash sont présentes dans un grand nombre de circuits visant des applications électroniques portatives. Leur non-volatilité et flexibilité en font des mémoires extrêmement populaires. Néanmoins, la fiabilité devient une caractéristique à améliorer en raison des besoins en surface grandissants et de leur intégration dans des applications sensibles. Des solutions de tolérance aux fautes peu coûteuses et faciles à intégrer doivent être mises en place. Tout d'abord, cette étude s'est portée sur l'analyse et l'étude de la fiabilité des Flash. Il fut l'occasion d'établir un modèle de fiabilité d'une cellule à grille flottante. Ce modèle a été ajusté suivant les paramètres issus d'une technologie Flash 180nm. Dans un second temps, deux techniques de tolérance aux fautes mêlant codes correcteurs d'erreurs et redondance ont été mises au point. La première technique, nommée correction d'erreurs par analyse de VT, fournit des capacités de correction accrues par l'analyse du niveau de programmation des cellules mémoire. Une étude mathématique puis une architecture de fiabilisation ont été proposées. Dans cette étude, on suppose que des ressources de redondance sont disponibles afin de réparer la mémoire lorsqu'une erreur est détectée. La seconde technique, appelée correction d'erreur hiérarchique, utilise des capacités de correction distribuées dans la mémoire Flash afin de réduire significativement le coût associé à une correction d'erreur avancée. Cette technique a été intégrée dans une architecture de fiabilisation disposant de ressources de redondance. Une étude basée sur les Chaines de Markov à Temps Continu a démontré l'efficacité de cette structure. Ces techniques constituent des solutions alternatives aux schémas standards utilisés dans l'industrie. Elles augmentent significativement le temps moyen à la défaillance du système sans faire exploser la surface requise à l'intégration une structure de tolérance
aux fautes.
aux fautes.
Loading...